Resistor Structure

ABSTRACT

Semiconductor structures and methods of forming the same are provided. A method according to an embodiment includes forming a conductive feature and a first conductive plate over a substrate, conformally depositing a dielectric layer over the conductive feature and the first conductive plate, conformally depositing a conductive layer over the conductive feature and the first conductive plate, and patterning the conductive layer to form a second conductive plate over the first conductive plate and a resistor, the resistor includes a conductive line extending along a sidewall of the conductive feature. By employing the method, a high-resistance resistor may be formed along with a capacitor regardless of the resolution limit of, for example, lithography.

PRIORITY DATA

This is a continuation application of U.S. patent application Ser. No.17/460,564, filed Aug. 30, 2021, and entitled “Resistor Structure,” theentirety of which is hereby incorporated by reference.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapidgrowth. Technological advances in IC materials and design have producedgenerations of ICs where each generation has smaller and more complexcircuits than the previous generation. This scaling down processgenerally provides benefits by increasing production efficiency andlowering associated costs. However, while transistors have scaled downconsiderably between generations, passive devices (e.g., resistors,capacitors, inductors, etc.) have not always progressed as quickly.

As the geometry size of IC devices decreases, passive devices thatrequire large surface areas may be formed in a back-end-of-line (BEOL)process. Metal-Insulator-Metal (MIM) capacitors and resistors are amongexamples of such passive devices. However, scaling of resistors as wellas formation of resistors with high resistance in advanced technologynodes are limited by the resolution of BEOL lithography processes. Thus,although existing structures and fabrication processes thereof have beengenerally adequate for their intended purposes, they have not beenentirely satisfactory in every aspect.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detaileddescription when read with the accompanying figures. It is emphasizedthat, in accordance with the standard practice in the industry, variousfeatures are not drawn to scale and are used for illustration purposesonly. In fact, the dimensions of the various features may be arbitrarilyincreased or reduced for clarity of discussion.

FIG. 1 is a flow chart of a method for fabricating an exemplarysemiconductor structure in accordance with embodiments of the presentdisclosure.

FIGS. 2-10, 12-13, and 16-25 are cross-sectional views of a portion of aworkpiece undergoing the method according to various aspects of thepresent disclosure.

FIGS. 11 and 14-15 are top views of a portion of the workpieceundergoing the method according to various aspects of the presentdisclosure.

FIG. 26 is a flow chart of another method for fabricating anotherexemplary semiconductor structure in accordance with embodiments of thepresent disclosure.

FIGS. 27-33 are cross-sectional views of a portion of another workpieceundergoing the method according to various aspects of the presentdisclosure.

FIGS. 34A-34B, 35A-35B, and 36A-36B are top views of exemplary shapes ofportions of the workpiece undergoing the method according to variousaspects of the present disclosure.

DETAILED DESCRIPTION

It is understood that the following disclosure provides many differentembodiments, or examples, for implementing different features of thepresent disclosure. Specific examples of components and arrangements aredescribed below to simplify the present disclosure. These are, ofcourse, merely examples and are not intended to be limiting. Forexample, the formation of a first feature over or on a second feature inthe description that follows may include embodiments, in which the firstand second features are formed in direct contact, and may also includeembodiments in which additional features may be formed between the firstand second features, such that the first and second features may not bein direct contact. In addition, the present disclosure may repeatreference numerals and/or letters in the various examples. Thisrepetition is for the sake of simplicity and clarity and does not initself dictate a relationship between the various embodiments and/orconfigurations discussed. Moreover, various features may be arbitrarilydrawn in different scales for the sake of simplicity and clarity.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. For example, if the device in the figures is turned over,elements described as being “below” or “beneath” other elements orfeatures would then be oriented “above” the other elements or features.Thus, the exemplary term “below” can encompass both an orientation ofabove and below. The apparatus may be otherwise oriented (rotated 90degrees or at other orientations) and the spatially relative descriptorsused herein may likewise be interpreted accordingly.

Still further, when a number or a range of numbers is described with“about,” “approximate,” and the like, the term is intended to encompassnumbers that are within a reasonable range considering variations thatinherently arise during manufacturing as understood by one of ordinaryskill in the art. For example, the number or range of numbersencompasses a reasonable range including the number described, such aswithin +/−10% of the number described, based on known manufacturingtolerances associated with manufacturing a feature having acharacteristic associated with the number. For example, a material layerhaving a thickness of “about 5 nm” can encompass a dimension range from4.25 nm to 5.75 nm where manufacturing tolerances associated withdepositing the material layer are known to be +/−15% by one of ordinaryskill in the art. Still further, the present disclosure may repeatreference numerals and/or letters in the various examples. Thisrepetition is for the purpose of simplicity and clarity and does not initself dictate a relationship between the various embodiments and/orconfigurations discussed.

Metal-Insulator-Metal (MIM) capacitors have been widely used infunctional circuits such as mixed signal circuits, analog circuits,Radio Frequency (RF) circuits, Dynamic Random-Access Memories (DRAMs),embedded DRAMs, and logic operation circuits. In system-on-chip (SOC)applications, different capacitors for different functional circuitshave to be integrated on a same chip to serve different purposes. Forexample, in mixed-signal circuits, capacitors are used as decouplingcapacitors and high-frequency noise filters. For DRAM and embedded DRAMcircuits, capacitors are used for memory storage, while for RF circuits,capacitors are used in oscillators and phase-shift networks for couplingand/or bypassing purposes. For microprocessors, capacitors are used fordecoupling. MIM capacitors are fabricated by a BEOL process to have alarger surface area. Other passive devices, such as resistors, are alsocommonly seen in functional circuits. For example, resistors may be usedto adjust signal levels, divide voltages, and terminate transmissionlines. Resistors formed near the first metal line may require additionallithography process steps. Such additional lithography process steps mayresult in increased cost.

The present disclosure relates to the formation of a semiconductorstructure, including resistors and capacitors. The method of the presentdisclosure forms a resistor along with an MIM capacitor. In someembodiments, the MIM capacitor includes three electrode plates, and theresistor is formed along with either a middle plate or a top electrodeplate. As the forming of the resistor shares a patterning process withthe capacitor, the fabrication of the semiconductor structure may besignificantly simplified, and the cost associated with the fabricationmay be advantageously reduced. In addition, by using the methoddescribed below, a resistor may be fabricated to have a small width andachieve a high resistance without high-resolution photolithography.

The various aspects of the present disclosure will now be described inmore detail with reference to the figures. In that regard, FIG. 1 is aflowchart illustrating a method 10 for fabricating a semiconductorstructure according to embodiments of the present disclosure. Method 10is described below in conjunction with FIGS. 2-25 , which arediagrammatic fragmentary cross-sectional views and/or top views of thesemiconductor structure at different stages of fabrication according toembodiments of the present disclosure. FIG. 26 is a flowchartillustrating a method 40 for fabricating another semiconductor structureaccording to embodiments of the present disclosure. Method 40 isdescribed below in conjunction with FIGS. 27-33 , which are diagrammaticfragmentary cross-sectional views of another semiconductor structure atdifferent stages of fabrication according to embodiments of the presentdisclosure. Methods 10 and 40 are merely examples and are not intendedto limit the present disclosure to what is explicitly illustrated inmethod 10 and/or method 40. Additional steps can be provided before,during, and after method 10 and/or method 40, and some steps describedcan be replaced, eliminated, or moved around for additional embodimentsof the method. Not all steps are described herein in detail for reasonsof simplicity.

Referring to FIGS. 1-8 , method 10 includes a block 12 where a workpiece200 is provided with lower contact features. The workpiece 200 includesvarious layers already formed thereon. Because a semiconductor structurewill be formed from the workpiece 200, workpiece 200 may be referred toas semiconductor structure 200 in suitable context. As shown in FIG. 2 ,the workpiece 200 includes a substrate 202, which may be made of siliconor other semiconductor materials such as germanium. The substrate 202also may include a compound semiconductor such as silicon carbide,gallium arsenic, indium arsenide, or indium phosphide. In someembodiments, the substrate 202 may include alloy semiconductor such assilicon germanium, silicon germanium carbide, gallium arsenic phosphide,or gallium indium phosphide. In some embodiments, the substrate 202 mayinclude an epitaxial layer, for example an epitaxial layer overlying abulk semiconductor. Various microelectronic components may be formed inor on the substrate 202, such as transistor components includingsource/drain features, gate structures, gate spacers, source/draincontacts, gate contacts, isolation structures including shallow trenchisolation (STI), or any other suitable components. In some embodiments,the transistor components may be formed in the substrate 202 in afront-end-of-line (FEOL) process.

As shown in FIG. 2 , the workpiece 200 also includes an interconnectlayer 210. The interconnect layer 210 may be a multi-layeredinterconnect (MLI) structure, which is formed over the substrate 202 andmay include multiple patterned dielectric layers and conductive layersthat provide interconnections (e.g., wiring) between the variousmicroelectronic components of the workpiece 200. There may beintermediate layers or components between the interconnect layer 210 andthe substrate 202, but in the interest of simplicity such layers orcomponents are not shown. In an embodiment, a thickness of theinterconnect layer 210 is between about 169 nanometers (nm) and about230 nm.

The interconnect layer 210 may include multiple conductive components aswell as an interlayer dielectric (ILD) component (or an intermetaldielectric (IMD) component) that partially or fully surrounds theconductive components. The conductive components may include contacts,vias, or metal lines. The ILD component may be a silicon oxide orsilicon oxide containing material where silicon exists in varioussuitable forms. As an example, the ILD component includes silicon oxideor a low-k dielectric material whose k-value (dielectric constant) issmaller than that of silicon oxide, which is about 4. In someembodiments, the low-k dielectric material includes a porousorganosilicate thin film such as SiOCH, tetraethyl orthosilicate (TEOS)oxide, un-doped silicate glass, doped silicon oxide such asborophosphosilicate glass (BPSG), fused silica glass (FSG),phosphosilicate glass (PSG), fluorine-doped silicon dioxide,carbon-doped silicon dioxide, porous silicon dioxide, porouscarbon-doped silicon dioxide, silicon carbonitride (SiCN), siliconoxycarbonitride (SiOCN), spin-on silicon based polymeric dielectrics, orcombinations thereof.

In an embodiment, a carbide layer 220 is deposited on the interconnectlayer 210. The deposition process includes chemical vapor deposition(CVD), physical vapor deposition (PVD), atomic layer deposition (ALD),or combinations thereof. In some embodiments, the carbide layer 220 hasa generally uniform thickness of between about 45 nm and about 70 nm.Any suitable type of carbide material such as silicon carbide (SiC) canbe used in the carbide layer 220.

In an embodiment, an insulating layer 230 is deposited on the carbidelayer 220. Any suitable deposition process may be used, including CVD,PVD, ALD, or combinations thereof. In some embodiments, the insulatinglayer 230 includes undoped silicon oxide. In some embodiments, theinsulating layer 230 includes undoped silicate glass (USG). In anembodiment, the interconnect layer 210, the carbide layer 220 and theinsulating layer 230 may be replaced with one or more interconnectstructures.

In an embodiment, an etch stop layer (ESL) 240 is deposited on theinsulating layer 230. In some embodiments, a thickness of the ESL 240 isbetween about 45 nm and about 55 nm. The ESL 240 may include siliconcarbonitride (SiCN), silicon oxycarbide (SiOC), silicon carbide (SiC),silicon oxycarbonitride (SiOCN), or silicon nitride (SiN), orcombinations thereof.

A first dielectric layer 250 may be deposited on the ESL 240. In someembodiments, the first dielectric layer 250 includes, for example,undoped silica glass (USG) or silicon oxide. In some embodiments, athickness of the first dielectric layer 250 is about 800 nm and about1000 nm.

The first dielectric layer 250 is then patterned to form trenches 251.In some implementations, patterning the first dielectric layer 250involves multiple processes. As illustrated in FIG. 3 , a siliconoxynitride (SiON) layer 252 is deposited on the first dielectric layer250. In some embodiments, a thickness of the SiON layer 252 is betweenabout 54 nm and about 66 nm. As shown in FIG. 4 , the SiON layer 252 ispatterned, for example, using a photolithography process. As shown inFIG. 5 , the first dielectric layer 250 is etched to form trenches 251therein using the SiON layer 252 as an etch mask. As shown in FIG. 6 ,the SiON layer 252 is removed after being used as an etch mask, leavingbehind a patterned first dielectric layer 250.

As shown in FIG. 7 , one or more lower contact features (such as 254 ba,254 b, and 254 c) are formed in the trenches 251 of the first dielectriclayer 250. Although the lower contact features 254 ba, 254 b, and 254 care disposed below upper contact features (to be discussed below), thelower contact features 254 ba, 254 b, and 254 c are sometimes referredto as top metal (TM) contacts because they may reside above transistorfeatures (not shown in figures herein). Each of the lower contactfeatures 254 ba, 254 b, and 254 c may include a barrier layer 256 a anda metal fill layer 256 b. Forming the lower contact features 254 ba, 254b, and 254 c involves multiple processes. In some embodiments, a barrierlayer 256 a is formed in each of the trenches 251, followed by thedeposition of a metal fill layer 256 b over the barrier layer 256 a inthe trenches. In some embodiments, the barrier layer 256 a includestitanium nitride, tantalum, tantalum nitride, or combinations thereof.In some embodiments, the metal fill layer 256 b includes a metal ormetal alloy such as copper, cobalt, nickel, aluminum, tungsten,titanium, or combinations thereof. In an embodiment, the metal filllayer 256 b is formed of copper. In some embodiments, the metal filllayer 256 b is formed by deposition or plating, followed by a chemicalmechanical planarization (CMP) process. In an embodiment, about 5% toabout 10% of the thickness of the metal fill layer 256 b is also removedby the CMP process.

As shown in FIG. 8 , a second dielectric layer 258 is deposited over thelower contact features 254 ba, 254 b, and 254 c. In some embodiments, athickness of the second dielectric layer 258 is about 65 nm and about 85nm. The second dielectric layer 258 may include silicon carbonitride(SiCN), silicon nitride (SiN), and/or or other suitable materials thatmay protect the lower contact features 254 ba, 254 b, and 254 c frombeing oxidized. Also, at block 12, a third dielectric layer 260 isdeposited over the second dielectric layer 258. In some embodiments, athickness of the third dielectric layer 260 is between about 300 nm andabout 500 nm. The third dielectric layer 260 may include an oxidematerial, such as undoped silica glass (USG), or other suitablematerial(s).

Referring to FIGS. 1 and 9-21 , method 10 includes blocks 14-22 where aresistor 271 a and a metal-insulator-metal (MIM) structure 271 b (shownin FIGS. 20-21 ) are formed over the third dielectric layer 260. Asshown in FIGS. 9-21 , forming the resistor 271 a and the MIM structure271 b involves multiple processes, including those for formation andpatterning of a bottom conducive layer 262, a middle conducive layer266, and a top conducive layer 270.

More specifically, referring to FIG. 9 , a bottom conductive layer 262is formed over the substrate in a resistor region 200 a and a capacitorregion 200 b. In some embodiments, the bottom conductive layer 262 maybe formed by performing a deposition process (e.g., a CVD process, a PVDprocess or an ALD process). In some embodiments, a thickness of thebottom conductive layer 262 is between about 30 nm and about 80 nm, suchas between about 35 nm and about 45 nm.

In some embodiments, the bottom conductive layer 262 may be made ofmetals. For example, the bottom conductive layer 262 may made ofaluminum, copper, tungsten, or another applicable material. In someembodiments, to substantially prevent or reduce electro-migration andoxygen diffusion, materials of forming the MIM structure's conductiveplates (e.g., the bottom conductive plate 262 b formed with reference toFIG. 10 , the middle conductive plate 266 c formed with reference toFIG. 16 , and the top conductive plate 270 formed with reference to FIG.19 ) may include a transition metal or a transition metal nitride suchas titanium, tantalum, titanium nitride, or tantalum nitride. In thisdepicted example, to further provide the MIM structure 271 b with a highswitching frequency, the materials of the bottom conductive layer 262,middle conductive layer 266 and top conductive layer 270 used to formthe corresponding conductive plates 262 b, 266 c and 270 in the MIMstructure 271 b include titanium nitride.

Referring to FIGS. 1 and 10 , method 10 includes a block 14 where apatterning process (e.g., a photolithography process and a subsequentetch process) is performed on the bottom conductive layer 262 to form aconductive feature 262 a in the resistor region 200 a and a bottomconductive plate 262 b in the capacitor region 200 b. The patterningprocess may be conducted by using, for example, lithography technologythat employs wavelengths range from about 190nm to about 250 nm.

An exemplary top view of the corresponding workpiece is shown in FIG. 11. In this depicted example, as shown in FIG. 11 , the conductive feature262 a is patterned to have a quadrilateral shape with four sidewalls263. As described below in detail, the shape of the conductive feature262 a may potentially affect a length of a to-be-formed conductive lineand thus the resistance of the to-be-formed resistor 271 a (shown inFIG. 15 ). Other exemplary shapes of the conductive feature 262 a arediscussed in further detail with reference to FIGS. 34A, 35A, and 36A.In some implementations, a width W (along the X direction) of theconductive feature 262 a may be between about 10 um and about 30 um, andthus the conductive feature 262 a may be formed without employing ahigh-resolution lithography (e.g., Extreme Ultraviolet (EUV)Lithography). A length L (along the Y direction) of the conductivefeature 262 a may be between about 50 um and 500 um. A correspondingresistance of the to-be-formed resistor 271 a (shown in FIG. 15 ) may begreater than 1000 a. It is understood by one of ordinary skill in theart that the width W and/or length L of the conductive feature 262 a maybe adjusted to obtain conductive lines (e.g., conductive lines 266 a and266 b shown in FIG. 15 ) with a different spacing and/or differentresistance.

Referring to FIGS. 1 and 12 , method 10 includes a block 16 where afirst insulator layer 264 is formed on the conductive feature 262 a andthe bottom conductive plate 262 b. In an embodiment, the first insulatorlayer 264 is conformally deposited to have a generally uniform thicknessover the top surface of the workpiece 200 (e.g., having substantiallythe same thickness on top and sidewall surfaces of the conductivefeature 262 a and the bottom conductive plate 262 b) and covers thesidewalls 263 of the conductive feature 262 a.

Referring to FIGS. 1 and 13 , method 10 includes a block 18 where amiddle conductive layer 266 is formed on the first insulator layer 264.In this depicted example, the middle conductive layer 266 is conformallydeposited to have a generally uniform thickness T₁ over the top surfaceof the workpiece 200 (e.g., having substantially the same thickness ontop and sidewall surfaces of the first insulator layer 264) and coversthe sidewalls 265 of the first insulator layer 264. In some embodiments,the middle conductive layer 266 may be formed by performing a depositionprocess (e.g., a CVD process, a PVD process or an ALD process).

The material of the middle conductive layer 266 may be same as thematerial of the bottom conductive layer 262. For example, the middleconductive layer 266 may be made of aluminum, copper, tungsten,titanium, tantalum, titanium nitride, tantalum nitride, or anotherapplicable material. In this depicted example, the middle conductivelayer 266 is also formed of titanium nitride. In some embodiments, athickness of the middle conductive layer 266 is less than 100 nm, forexample, between about 30 nm and about 80 nm. In this depicted example,the thickness T₁ of the middle conductive layer 266 may be between about35 nm and about 45 nm.

As described above, forming a resistor on the same substrate with thecapacitor may advantageously improve the process integration and reducecost. Some applications may require resistors with high resistances. Asindicated by the equation (1) below, the resistance of a resistor is notonly determined by the material of conductive lines used to form theresistor, but also related to the size (e.g., length and cross-sectionalarea) of the conductive lines. For a given resistor material, the sizeof a conductive line can be configured to arrive at resistors ofdifferent resistances. Although the resistivity of titanium nitride islower than, for example, tantalum nitride, a titanium nitride conductiveline can be fabricated to have a smaller cross-sectional area and agreater length to achieve a resistance comparable to the tantalumnitride resistor.

$\begin{matrix}{{R = {\frac{\rho L}{A} = \frac{\rho L}{WT}}},} & {{equation}(1)}\end{matrix}$

wherein R is the resistance, ρ is the resistivity of the materialforming the conductive line, L is the length of the conductive line, Ais the cross-sectional area of the conductive line, W is the width ofthe conductive line, and T is the thickness of the conductive line. Asdescribed below in more detail, a resistor according to the presentdisclosure is formed along with a middle conductive plate of the MIMstructure 271 b and attains a high resistance without employing ahigh-resolution lithography (e.g., Extreme Ultraviolet (EUV)Lithography).

Referring to FIGS. 1 and 14-16 , method 10 includes a block 20 where themiddle conductive layer 266 is patterned to form a resistor 271 a and amiddle conductive plate 266 c of the MIM structure 271 b. Morespecifically, as shown in FIG. 14 , photoresist patterns and/or hardmask patterns 267 a, 267 b and 267 c are formed over the middleconductive layer 266 to cover exemplary three regions (i.e., a firstregion, a second region, and a third region) of the middle conductivelayer 266. In this depicted example, the patterns 267 a and 267 b extendalong two opposing sidewalls 263 of the conductive feature 262 a, whichis now covered by the first insulator layer 264 and the middleconductive layer 266. While the patterns 267 a and 267 b in FIG. 14extend lengthwise along the X direction, they may extend lengthwisealong the Y direction in alternative embodiments not explicitly shown inthe figures.

After forming the photoresist patterns and/or hard mask patterns 267 a,267 b and 267 c, an etch process (not shown) is performed to remove theuncovered middle conductive layer 266 (e.g., portions of middleconductive layer 266 that are not covered by the photoresist patternsand/or hard mask patterns 267 a, 267 b and 267 c). For example, theportion of the middle conductive layer 266 that is directly over theconductive feature 262 a is removed. The portion of the middleconductive layer 266 that is disposed between the resistor 271 a and themiddle conductive plate 266 c is also removed. In some embodiments, theetch process may include a dry etch process and may be anisotropic. Insome embodiments, the first insulator layer 264 may be used as an etchstop layer during this etch process.

An exemplary top view of the workpiece 200 after undergoing the aboveetch process is shown in FIG. 15 . After the etch process, thepreviously covered first region and second region (i.e., regions coveredby the patterns 267 a and 267 b shown in FIG. 14 ) of the middleconductive layer 266 may function as a first electrode 266 d and asecond electrode 266 e of the resistor 271 a, respectively. In thisdepicted example, the first electrode 266 d and the second electrode 266e extend lengthwise along the X direction.

Still referring to FIG. 15 , after the etch process, a first conductiveline 266 a is formed over and extending along a first sidewall of theconductive feature 262 a, and a second conductive line 266 b is formedover and extending along a second sidewall the conductive feature 262 a.The first conductive line 266 a and the second conductive line 266 b arespaced apart from and insulated from the conductive feature 262 a by thefirst insulator layer 264. In this depicted example, the firstconductive line 266 a and the second conductive line 266 b are along theY direction. The two conductive lines 266 a and 266 b extend between thefirst electrode 266 d and the second electrode 266 e and each of theconductive lines 266 a and 266 b has a proximal end 266 f and a distalend 266 g. The first electrode 266 d directly contacts the proximal ends266 f of the conductive lines 266 a and 266 b, and the second electrode266 e directly contacts the distal ends 266 g of the conductive lines266 a and 266 b. Because the two conductive lines 266 a and 266 b arecoupled to the first electrode 266 d and the second electrode 266 e inparallel, the resistance of the resistor 271 a may be one half (½) ofthe resistance of the conductive line 266 a or the conductive line 266b.

As shown in FIG. 15 , the length of the first/second conductive line 266a/266 b along the Y direction bears a relationship with the length ofthe conductive feature 262 a along the Y direction. The longer theconductive feature 262 a along the Y direction, the longer is the lengthof the first/second conductive line 266 a/266 b along the Y direction.In some implementations, the length of the first/second conductive line266 a/266 b along the Y direction may be substantially equal to a sum ofthe length L of the conductive feature 262 a along the Y direction andtwice the thickness of the first insulator layer 264. A distance betweenthe first and second conductive lines 266 a-266 b along the X directionmay be substantially equal to a sum of the width W of the conductivefeature 262 a along the X direction and twice the thickness of the firstinsulator layer 264. A width W₁ of the first/second conductive line 266a/266 b is substantially equal to the deposition thickness T₁ of themiddle conductive layer 266. In some embodiments, the width W₁ of theconductive line 266 a/266 b is less than 100 nm, for example, aboutbetween 30 nm and about 80 nm. In this depicted example, the width W₁ ofthe conductive line 266 a/266 b may be between about 35 nm and about 45nm. By forming the first and second conductive lines 266 a-266 b withsmall widths along the X direction and a longer length along the Ydirection, a high-resistance resistor may be then obtained. In someembodiments, the resistor 271 a may provide a resistance ranged fromabout 500Ω to about 5 MΩ, for example.

In addition, still referring to FIG. 15 , the previously covered thirdregion (i.e., the region covered by the pattern 267 c shown in FIG. 14 )of the middle conductive layer 266 functions as a middle conductiveplate 266 c of the MIM structure 271 b. Thus, without applying ahigh-resolution lithography, sidewall spacers (e.g., conductive lines266 a and 266 b shown in FIG. 16 ) with small widths W₁ may be formed attwo parallel sidewalls of the first insulator layer 264. In other words,formation of the conductive lines 266 a and 266 b does not requireforming a photoresist pattern that selectively exposes or covers theareas where the of the conductive lines 266 a and 266 b are formed. Anexemplary cross-sectional view of the workpiece 200 taken along lineA-A′ after the etch process is shown in FIG. 16 .

As discussed with reference to FIGS. 13-16 , the conductive lines 266a-266 b and the electrodes 266 d-266 e of the resistor 271 a are formedin the same patterning process (e.g., a photolithography process and thesubsequent etch process) and formed of the same material. Moreparticularly, in this depicted example, the resistor 271 a is formed ofthe same material as the middle conductive plate 266 c by simultaneouslypatterning the middle conductive layer 266.

As stated with reference to the equation (1), besides material andcross-sectional area, the resistance of the resistor 271 a is also afunction of the lengths of the conductive lines 266 a and 266 b. Asdiscussed with references to FIGS. 10-15 , the lengths of the conductivelines 266 a and 266 b are functions of the shape and size of thesidewalls 265 of the first insulator layer 264 and thus functions of theshape and size of the sidewalls 263 of the conductive feature 262 a.Thus, by configuring the shape and size of the conductive feature 262 a,resistance of the resistor 271 a may be configured accordingly. In thisdepicted example of forming the resistor 271 a, as shown in FIG. 11 ,the conductive feature 262 a is patterned to have a quadrilateral shape.Other exemplary shapes of the conductive feature 262 a and correspondingshapes of the conductive lines 266 a-266 b are discussed in furtherdetail with reference to FIGS. 34A-34B, 35A-35B, and 36A-36B.

Referring to FIGS. 1 and 17-19 , method 10 includes a block 22 where asecond insulator layer 268 and a top conductive plate 270 are formedover the workpiece. More specifically, the second insulator layer 268 isdisposed over the resistor 271 a, the middle conductive plate 266 c, andportions of the first insulator layer 264 (e.g., portions of the firstinsulator layer 264 that are not covered by the resistor 271 a and themiddle conductive plate 266 c). An exemplary cross-sectional view of theworkpiece 200 taken along line A-A′ after the deposition of the secondinsulator layer 268 is shown in FIG. 17 . An exemplary cross-sectionalview of the workpiece 200 taken along line B-B′ after the deposition ofthe second insulator layer 268 is shown in FIG. 18 . In this embodiment,the second insulator layer 268 is conformally deposited to have agenerally uniform thickness over the top surface of the workpiece 200(e.g., having substantially the same thickness on top surfaces of theresistor 271 a, the middle conductive plate 266 c, and portions of thefirst insulator layer 264 not covered by the resistor 271 a and themiddle conductive plate 266 c) and covers the sidewalls of the resistor271 a and the middle conductive plate 266 c.

After depositing the second insulator layer 268, a patterned topconductive plate 270 is formed over the middle conductive plate 266 c inthe capacitor region 200 b. The top conductive plate 270 may be formedin a way similar to that used to form the bottom conductive plate 262 b,but the pattern of the top conductive plate 270 may be different fromthat of the bottom conductive plate 262 b. An exemplary cross-sectionalview of the workpiece 200 taken along line A-A′ after the formation ofthe top conductive plate 270 is shown in FIG. 19 .

In some embodiments, a thickness of the top conductive plate 270 may beless than 100 nm, for example, between about 30 nm and about 80 nm. Inthis depicted example, a thickness of the top conductive plate 270 maybe between about 35 nm and about 45 nm. The top conductive plate 270 maybe formed of the same material to the bottom conductive plate 262 band/or the middle conductive plate 266 c. For example, the topconductive plate 270 may be made of aluminum, copper, tungsten,titanium, tantalum, titanium nitride, tantalum nitride, or anotherapplicable material. In this depicted example, the top conductive plate270 is also formed of titanium nitride. In some embodiments, the topconductive plate 270 may be formed by performing a deposition process(e.g., a CVD process, a PVD process or an ALD process).

As illustrated in FIG. 19 , the MIM structure 271 b includes multiplemetal layers including the bottom conductive plate 262 b, the middleconductive plate 266 c, and the top conductive plate 270. The MIMstructure 271 b also includes multiple insulator layers including thefirst insulator layer 264 disposed between the bottom conductive plate262 b and the middle conductive plate 266 c, as well as the secondinsulator layer 268 disposed between the middle conductive plate 266 cand the top conductive plate 270. The MIM structure 271 b is used toimplement one or more capacitors, which may be connected to otherelectric components such as transistors. The multi-layer MIM structure271 b allows capacitors to be closely packed together in both verticaland lateral directions, thereby reducing the amount of lateral spaceneeded for implementing capacitors. As a result, the MIM structure 271 bmay accommodate super high-density capacitors.

In some embodiments, to increase capacitance values, the first insulatorlayer 264 and/or the second insulator layer 268 use high-k dielectricmaterial(s) whose k-value is greater than that of silicon oxide. Thefirst and second insulator layers 264 and 268 may be relatively thin toincrease capacitance values. However, minimal thicknesses for the firstand second insulator layers 264 and 268 are maintained to avoidpotential breakdown of the capacitors in the MIM structure 271 b (e.g.,when two capacitor plates have high potential difference, current mayleak between the plates, causing breakdown). In some embodiments, eachof the first and second insulator layers 264 and 268 is about 4 nm toabout 20 nm thick, such as between about 4 nm and about 10 nm. In someimplementations, each of the first insulator layer 264 and the secondinsulator layer 268 may be formed of zirconium oxide (ZrO₂), hafniumoxide (HfO₂), aluminum oxide (Al₂O₃ tantalum oxide (TaO₅), silicon oxide(SiO₂), or titanium oxide (TiO₂). Further, to optimize the capacitorperformance, in some embodiments, the first insulator layer 264 (or thesecond insulator layer 268) is a tri-layer structure including, frombottom to top, a first zirconium oxide (ZrO₂) layer, an aluminum oxide(Al₂O₃) layer, and a second zirconium oxide (ZrO₂) layer, where each ofthe layers is about 2 nm to about 5 nm thick. In some embodiments, atotal thickness of the ZrO₂/Al₂O₃/ZrO₂ (ZAZ) dielectric may range from 4nm to 10 nm, for example.

Referring to FIGS. 1 and 20-21 , method 10 includes a block 24 where afourth dielectric layer 272 is deposited over the resistor 271 a and theMIM structure 271 b. FIG. 20 depicts a cross-sectional view of theworkpiece after the formation of the fourth dielectric layer 272 takenalong line A-A′ in FIG. 15 . FIG. 21 depicts a cross-sectional view ofthe workpiece after the formation of the fourth dielectric layer 272taken along line B-B′ in FIG. 15 . In some embodiments, a thickness ofthe fourth dielectric layer 272 may be between about 400 and about 500nm. In some embodiments, the fourth dielectric layer 272 may include anoxide material, such as undoped silica glass, or other suitablematerial(s). In some embodiments, the fourth dielectric layer 272 isformed by depositing about 900 to about 1000 nm of the oxide material,followed by a CMP process to reach the final thickness.

As shown in FIGS. 20-21 , the resistor 271 a (including the conductivelines 266 a-266 b and the electrodes 266 d-266 e) and the MIM structure271 b are sandwiched between the third dielectric layer 260 and thefourth dielectric layer 272, which may have the same material and/or thesame thickness. In some embodiments, the second dielectric layer 258,the third dielectric layer 260, the resistor 271 a and the MIM structure271 b, and the fourth dielectric layer 272 are regarded as parts of afirst multi-layer passivation structure 273. Alternatively, if theresistor 271 a and the MIM structure 271 b are not present in thepassivation structure 273, the third dielectric layer 260 and the fourthdielectric layer 272 may be combined as a single dielectric layer (e.g.,about 900 to about 1100 nm thick) over the second dielectric layer 258.

Referring to FIGS. 1 and 22 , method 10 includes a block 26 where one ormore openings (such as openings 274 a, 274 b, and 274 c) are formed toexpose surfaces of the electrodes of the resistor 271 a and lowercontact features 254 b and 254 a. In some embodiments, the openings 274a-274 c may be formed in multiple steps. For example, the opening 274 amay be formed by penetrating the fourth dielectric layer 272 and thesecond insulator layer 268 to expose a top surface of the firstelectrode 266 d. Another opening (not shown) may be formed similarly toexpose a top surface of the second electrode 266 e. Openings 274 b and274 c may be formed by penetrating through, from top to bottom, thefourth dielectric layer 272, the MIM structure 271 b, the thirddielectric layer 260, and the second dielectric layer 258. In someimplementations, one or more rinse or cleaning processes may beperformed to clean the exposed conductive surfaces, such as thesidewalls through the MIM structure 271 b, the exposed portions of thelower contact features 254 b and 254 c, and the exposed portions of theelectrodes 266 d and 266 e.

In some other embodiments, the openings 274 a-274 c may be formedsimultaneously. In these embodiments, the openings 274 a-274 c allterminate on or in one of the lower contact features 254 a, 254 b, and254 c. For example, the openings (such as opening 274 a), formed in theresistor region 200 a, may also be formed to penetrate the fourthdielectric layer 272, the second insulator layer 268, the correspondingfirst electrode 266 d/the second electrode 266 e, the third dielectriclayer 260, and the second dielectric layer 258.

Referring to FIGS. 1 and 23 , method 10 includes a block 28 where one ormore upper contact features (such as 276 a, 276 b, and 276 c) are formedin and over the openings 274 a, 274 b, and 274 c, respectively. Theupper contact features 276 a, 276 b, and 276 c include contact vias thatfill the openings 274 a, 274 b, and 274 c and may be referred to ascontact via, metal vias, or metal lines.

At least the upper portion of the upper contact features 276 a, 276 b,and 276 c may be part of a redistribution layer (RDL) to reroute bondconnections between upper and lower layers. The upper contact feature276 a penetrates through, from top to bottom, the fourth dielectriclayer 272 and the second insulator layer 268 and makes electricalcontact with the first electrode 266 d of the resistor 271 a. Similarprocesses may be performed to form an upper contact feature thatelectrically contacts with the second electrode 266 e of the resistor271 a.

The upper contact features 276 b and 276 c each penetrate through, fromtop to bottom, the fourth dielectric layer 272, the MIM structure 271 b,the third dielectric layer 260, and the second dielectric layer 258. Theupper contact features 276 b and 276 c make electrical contact with thelower contact features 254 b and 254 c, respectively. The upper contactfeature 276 b is a middle-plate (MP) contact via that is electricallycoupled to the middle conductive plate 266 c but is electricallyinsulated from the bottom conductive plate 262 b and the top conductiveplate 270. The upper contact feature 276 c is a top-plate-bottom-plate(TPBP) contact via that is electrically coupled to the bottom conductiveplate 262 b and the top conductive plate 270 but is electricallyinsulated from the middle conductive plate 266 c.

In some embodiments, to form the one or more upper contact features(such as 276 a, 276 b, and 276 c), a barrier layer 277 a is firstconformally deposited over the fourth dielectric layer 272 and into theopenings 274 a, 274 b, and 274 c using a suitable deposition technique,such as an ALD process, a PVD process or a CVD process, and then a metalfill layer 277 b is deposited over the barrier layer 277 a using asuitable deposition technique, such as an ALD process, a PVD process ora CVD process. In some embodiments, the barrier layer 277 a may beformed of the same material of the conductive layer 262, conductivelayer 266, and/or conductive layer 270. In those embodiments, thebarrier layer 277 a may be formed of titanium, tantalum, titaniumnitride, or tantalum nitride. In one embodiment, the barrier layer 277 aincludes tantalum nitride. The metal fill layer 277 b may be formed ofcopper, aluminum, or an alloy thereof. In some instances, the metal filllayer 277 b for the upper contact features may include about 95% ofaluminum and 5% of copper. The deposited barrier layer 277 a and themetal fill layer 277 b are then patterned to form upper contact features276 a, 276 b, and 276 c, as illustrated in the example in FIG. 23 .

In some embodiments, the barrier layer 277 a and the metal fill layer277 b are patterned in a two-stage or multiple-stage etch process. Inembodiments represented in FIG. 23 , portions of the upper contactfeatures 276 a, 276 b, and 276 c above the fourth dielectric layer 272have substantially straight sidewalls. In other embodiments notexplicitly shown in FIG. 23 , portions of the upper contact features 276a, 276 b, and 276 c above the fourth dielectric layer 272 have taperedsidewalls. While not shown in the figures, the upper contact features276 a, 276 b, and 276 c may have a substantially square shape, acircular shape, an oval shape, a racetrack shape, a polygon shape, or arectangular shape when viewed along the Z direction.

Referring to FIGS. 1 and 24 , method 100 includes a block 30 where apassivation structure is formed over upper contact features 276 a, 276b, and 276 c and over the fourth dielectric layer 272. As shown in FIG.24 , a first passivation layer 280 is formed over the workpiece 200,including over the upper contact features 276 a, 276 b, and 276 c andthe fourth dielectric layer 272. In some embodiments, the firstpassivation layer 280 may include one or more plasma-enhanced oxidelayers, one or more undoped silica glass layers, or a combinationthereof. The first passivation layer 280 may be formed using CVD,spin-on coating, or other suitable technique. In some implementations,the first passivation layer 280 may be formed to a thickness betweenabout 1000 nm and about 1400 nm, such as between about 1100 nm and 1300nm.

A second passivation layer 282 is formed over the first passivationlayer 280. In some embodiments, the second passivation layer 282 mayinclude silicon nitride (SiN) and may be formed by CVD, PVD or asuitable method to a thickness between about 600 nm and about 800 nm,such as between about 650 nm and 750 nm.

Referring to FIGS. 1 and 25 , method 10 includes a block 32 wherefurther processes may be performed. Such further processes may includeformation of the openings 284 through the first passivation layer 280and the second passivation layer 282, deposition of one or morepolymeric material layers, patterning of the one or more polymericmaterial layers, deposition of an under-bump-metallurgy (orunder-bump-metallization, UBM) layer, deposition of a copper-containingbump layer, deposition of a cap layer, deposition of a solder layer, andreflowing of the solder layer. These further processes form contactstructures for connection to external circuitry.

In methods and structures depicted above, the resistor 271 a is formedalong with the middle conductive plate 266 c of the MIM structure 271 b.However, the resistor 271 a may also be formed along with anotherconductive plate of the MIM structure. For example, in the method 40(illustrated in the exemplary flowchart in FIG. 26 and described belowin conjunction with FIGS. 27-33 ), a resistor 471 a according to thepresent disclosure is formed along with a top conductive plate of a MIMstructure 471 b.

Referring to FIGS. 26-27 , method 40 includes a block 42 where aworkpiece 400 is provided with lower contact features 254 a, 254 b and265 c. The workpiece 400 may be formed in similar processes as discussedabove with reference to FIGS. 2-8 .

Still referring to FIGS. 26-27 , method 40 includes a block 44 where apatterned bottom conductive plate 462 is formed on the workpiece in acapacitor region 400 b. The bottom conductive plate 462 may be formed ina way similar to that used to form the bottom conductive plate 262 bdiscussed with reference to FIGS. 9-10 . It is noted that, differentfrom block 14 of method 10, no conductive feature is formed in aresistor region 400 a at block 44 of method 40.

Still referring to FIGS. 26-27 , method 40 includes a block 46 where afirst insulator layer 464 is formed over the bottom conductive plate 462in both the resistor region 400 a and the capacitor region 400 b. Thefirst insulator layer 464 may be formed in a way similar to that used toform the first insulator layer 264 as described above with reference toFIG. 12 . For example, the first insulator layer 464 is conformallydeposited to have a generally uniform thickness over the top surface ofthe workpiece 400 (e.g., having substantially the same thickness on topand sidewall surfaces of the bottom conductive plate 462) and coverssidewalls of the bottom conductive plate 462.

Now referring to FIGS. 26 and 28 , method 40 includes a block 48 where aconductive feature 466 a is formed in the resistor region 400 a and amiddle conductive plate 466 b is formed in the capacitor region 400 b.In some embodiments, the formation of the conductive feature 466 a andthe middle conductive plate 466 b may involve forming a middleconductive layer (not shown), and then patterning the middle conductivelayer to form the conductive feature 466 a and the middle conductiveplate 466 b. The middle conductive layer may be formed in a way similarto that used to form the middle conductive layer 266 as described abovewith reference to FIG. 13 . The top view of the workpiece 400 afterpatterning the middle conductive layer may be similar to the top view ofthe workpiece 200 discussed above with reference to FIG. 11 . Asdescribed above, the conductive feature 466 a and the middle conductiveplate 466 b may be customized to have different shapes and dimensions tomeet design needs. For example, the conductive feature 466 a may haveshapes similar to conductive features 262 a′, 262 a″ or 262 c shown inFIG. 34A, 35A or 36 .

Referring to FIGS. 26 and 29 , method 40 includes blocks 50 and 52 wherea top conductive layer is formed and then patterned over the workpiece400. In an embodiment, the top conductive layer (not shown) isconformally deposited to have a generally uniform thickness T₂ over thetop surface of the workpiece 400. In some embodiments, the thickness T₂of the top conductive layer is less than 100 nm, for example, betweenabout 30 nm and about 80 nm. In this depicted example, a thickness ofthe top conductive layer may be between about 35 nm and about 45nm. Thematerial of the top conductive layer may be same to the bottomconductive layer 462. For example, the top conductive layer may be madeof aluminum, copper, tungsten, titanium, tantalum, titanium nitride,tantalum nitride, or another applicable material. In this depictedexample, the top conductive layer is also formed of titanium nitride.

As shown in FIG. 29 , the top conductive layer is patterned to form aresistor 471 a and a top conductive plate 470 c of the MIM structure 471b in a way similar to that used to form the resistor 271 a and middleconductive plate 266 c as described above with reference to FIGS. 13-16. Similarly, the resistor 471 a includes two conductive lines 470 a, 470b and two electrodes (electrode 470 d shown in FIG. 31 , the other isnot explicitly shown in the figures). The two conductive lines 470 a and470 b are spaced apart from and insulated from the conductive feature466 a by the second insulator layer 468. The two electrodes (electrode470 d shown in FIG. 31 ) may extend lengthwise along the X direction.Thus, without applying a high-resolution lithography, conductive lines470 a and 470 b with small widths may be formed at the sidewalls of thesecond insulator layer 468. In other words, formation of the conductivelines 470 a and 470 b does not require forming a photoresist patternthat selectively exposes or covers the areas where the conductive lines470 a and 470 b are formed.

Referring to FIG. 29 , the width W₂ of the conductive lines 470 a and470 b may be substantially equal to the deposition thickness T₂ of thetop conductive layer 470. In some embodiments, the width W₂ of theconductive lines 470 a and 470 b is less than 100 nm, for example,between about 30 nm and about 80 nm, such as between about 35 nm andabout 45 nm. By forming the conductive lines 470 a and 470 b with asmall width, high resistance may be then obtained. In some embodiments,the resistor 471 a may provide a resistance ranged from about 500Ω toabout 5 MΩ, for example.

In some embodiments, the first insulator layer 464 and/or the secondinsulator layer 468 use high-k dielectric material(s) whose k-value isgreater than that of silicon oxide. In some implementations, the firstinsulator layer 464 and/or the second insulator layer 468 is a tri-layerstructure including, from bottom to top, a first zirconium oxide (ZrO₂)layer, an aluminum oxide (Al₂O₃) layer, and a second zirconium oxide(ZrO₂) layer, and a total thickness of the ZrO₂/Al₂O₃/ZrO₂ (ZAZ)dielectric may range from 4 nm to 10 nm, for example.

Referring to FIGS. 26 and 30-31 , method 40 includes a block 54 where afourth dielectric layer 472 is deposited over the resistor 471 a and theMIM structure 471 b. FIG. 30 depicts a cross-sectional view of theworkpiece 400 after the formation of the fourth dielectric layer 472taken along a line that cuts across the conductive lines 470 a and 470 bin the X direction (similar to the line A-A′ in FIG. 15 ). FIG. 31depicts a cross-sectional view of the workpiece after the formation ofthe fourth dielectric layer 472 taken along a line that cuts across theelectrode 470 d in the X direction (similar to the line B-B′ in FIG. 15). The formation of the fourth dielectric layer 472 may be similar tothat used to form the fourth dielectric layer 272 as described withreference to FIGS. 20-21 .

Referring to FIGS. 26 and 32 , method 40 includes blocks 56 and 58 whereone or more openings (not shown) are formed using a plurality of etchprocesses. Then, one or more upper contact features (such as uppercontact features 476 a-476 c) are formed in the openings. In thisdepicted example, the openings (not shown) in the resistor region 400 aand the in the capacitor region 400 b may be formed simultaneously. Forexample, the openings in the resistor region 400 a may be formed bypenetrating the fourth dielectric layer 472, the corresponding electrode(such as the electrode 470 d), the second insulator layer 468, the thirddielectric layer 260, and the second dielectric layer 258. Openings inthe resistor region 400 a may be formed by penetrating through, from topto bottom, the fourth dielectric layer 472, the MIM structure 471 b, thethird dielectric layer 260, and the second dielectric layer 258. In someimplementations, one or more rinse or cleaning processes may beperformed to clean the exposed conductive surfaces, such as thesidewalls through the MIM structure 271 b, the exposed portions of thelower contact features 254 ba, 254 b and 254 c, and the exposed portionsof the electrodes (electrode 470 d shown in FIG. 32 ). In some otherembodiments, the formation of the openings and upper contact features476 a-476 c may be similar to that used to form the openings 274 a-274 cand the upper contact features 276 a-276 c as described with referenceto FIGS. 22-23 .

Referring to FIGS. 26 and 33 , method 40 includes a block 60 where apassivation structure is formed over upper contact features 476 a, 476b, and 476 c and over the fourth dielectric layer 472. As shown in FIG.33 , a first passivation layer 480 and a second passivation layer 482are formed over the workpiece 400. The formation of the firstpassivation layer 480 and a second passivation layer 482 may be similarto that used to form the first passivation layer 280 and a secondpassivation layer 282 as described with reference to FIG. 24 .

Still referring to FIGS. 26 and 33 , method 40 includes a block 62 wherefurther processes may be performed. Such further processes may includeformation of the openings 484 through the first passivation layer 480and the second passivation layer 482, deposition of one or morepolymeric material layers, patterning of the one or more polymericmaterial layers, deposition of an under-bump-metallurgy (orunder-bump-metallization, UBM) layer, deposition of a copper-containingbump layer, deposition of a cap layer, deposition of a solder layer, andreflowing of the solder layer. These further processes form contactstructures for connection to external circuitry.

As discussed above, the shape and size of the conductive features 262a/466 a may affect the shape and length of the conductive lines 226a/266 b or 470 a/470 b, and thus affect the resistance of the resistor271 a/471 a. Three exemplary shapes for the conducive feature 262 a andcorresponding shapes of the conductive lines 226 a/266 b are shown withreference to FIGS. 34A, 35A, 36A and FIGS. 34B, 35B, 36B, respectively.Similar shapes can also be applied to the patterning of the conductivefeatures 466 a to obtain corresponding conductive lines and meetdifferent requirements for the resistor 471 a.

For example, as shown in FIG. 34A, a conductive feature 262 a′ has ahexagon shape. Thus, after patterning the middle conductive layer 266,conductive lines 266 a′/266 b′ would extend along sidewalls of thehexagon, as shown in FIG. 34B. Comparing to the shape of the conductivefeature 262 a shown in FIG. 11 , lengths of the conductive lines 266a′/266 b′ are increased, and the conductive lines 266 a′/266 b′ arelonger than the conductive lines 266 a/266 b when the area of theconductive feature 262 a′ is substantially equal to the area of theconductive feature 262 a. Thus, due to the equation (1), a resistor witha larger resistance may be obtained.

As shown in FIG. 35A, a conductive feature 262 a″ has a serpentineshape. Corresponding shapes of the conductive lines 266 a″/266 b″ areshown in FIG. 35B. As shown in FIG. 36A, a conductive feature 262 a″′has a shape of a letter “I”. Corresponding shapes of the conductivelines 266 a″′/266 b″′ are shown in FIG. 36B. Although a limited numberof shapes are shown, the present disclosure may not be so limited. Theconductive feature 262 a may also be patterned to other shapes, such asround, oval, or irregular shapes, to change lengths of the conductivelines and thus resistance of the resistor 471 a.

Methods and semiconductor structures according to the present disclosureprovide advantages. For example, methods of the present disclosure forma high-resistance resistor along with a MIM structure without employinghigh-resolution photolithography. As such, methods of the presentdisclosure may form resistor structures at a reduced cost.

One aspect of the present disclosure involves a method. The methodincludes forming a conductive feature and a first conductive plate overa substrate, conformally depositing a dielectric layer over theconductive feature and the first conductive plate, conformallydepositing a conductive layer over the conductive feature and the firstconductive plate, and patterning the conductive layer to form a secondconductive plate over the first conductive plate and a conductive lineextending along a sidewall of the conductive feature.

In some embodiments, the patterning includes removing the conductivelayer directly over the conductive feature. In some embodiments, thepatterning includes physically separating the conductive line and thesecond conductive plate. In some embodiments, the sidewall is a firstsidewall, the patterning includes forming a first electrode extendingalong a second sidewall of the conductive feature and a second electrodeextending along a third sidewall of the conductive feature, the firstelectrode electrically contacts a proximal end of the conductive lineand the second electrode electrically contacts a distal end of theconductive line. In some implementations, after the patterning, theconductive line and the first electrode are isolated from the conductivefeature by the dielectric layer.

In some implementations, the method also includes depositing apassivation layer over the second conductive plate, the conductive line,the first electrode, and the second electrode, and patterning thepassivation layer to form a first opening and a second opening to exposethe first electrode and the second electrode, respectively.

In some instances, the substrate includes an interconnect structure, andthe patterning of the passivation layer also forms a third openingthrough the second conductive plate to expose a lower contact featureelectrically coupled to the interconnect structure. In some instances,the conductive layer, the conductive feature, and the first conductiveplate include titanium nitride.

In some implementations, the method also includes depositing a topdielectric layer over the second conductive plate and the conductiveline after the patterning of the conductive layer and forming a thirdconductive plate over the second conductive plate after the depositingof the top dielectric layer.

In some implementations, the method also includes forming a thirdconductive plate over the substrate before the forming of the conductivefeature and the first conductive plate and depositing a bottomdielectric layer over the third conductive plate, the conductive featureand the first conductive plate are formed over the bottom dielectriclayer.

Another aspect of the present disclosure involves a method. The methodincludes forming a conductive feature over a substrate, conformallydepositing a dielectric layer over the conductive feature, conformallydepositing a conductive layer over the dielectric layer, and performingan etch process on the conductive layer to form a first conductive lineand a second conductive line extending along a first sidewall and asecond sidewall of the conductive feature, and form a first electrodeelectrically contacts proximal ends of the two conductive lines and asecond electrode electrically contacts distal ends of the two conductivelines.

In some embodiments, the method also includes providing a photoresistover the conductive layer to cover a predetermined region before theperforming of the etch process, the etch process forms the firstelectrode and the second electrode in the predetermined region. In someembodiments, the method also includes forming a first conductive plateover the substrate before the conformally depositing of the dielectriclayer, the performing of the etch process further forms a secondconductive plate over the first conductive plate.

In some implementations, a width of the first conductive line is lessthan about 100 nm. In some embodiments, the conductive layer comprisestitanium nitride, copper, cobalt, or tungsten. In some instances, theconductive feature may substantially have a quadrangle shape, a hexagon,or may have a shape of a letter I.

Still another aspect of the present disclosure involves a semiconductorstructure. The semiconductor structure includes a resistor disposed on asurface. The resistor includes a first electrode and a second electrode,and two conductive lines extending between the first electrode and thesecond electrode. The semiconductor structure also includes a capacitordisposed on the surface. The capacitor includes a first plate conductor,and a second plate conductor over the first plate conductor, theresistor and the second plate conductor include a same material.

In some embodiments, the material includes titanium nitride, copper,cobalt, or tungsten. In some embodiments, a width of each of the twoconductive lines is substantially equal to a thickness of the secondplate conductor. In some implementations, the capacitor also includes abottom plate conductor under the first plate conductor.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A semiconductor structure, comprising: asubstrate comprising a first region and a second region; a firstmaterial layer disposed directly over the first region and comprising afirst sidewall and a second sidewall opposite the first sidewall along afirst direction; a conformal second material layer disposed over thefirst material layer and the substrate, wherein the conformal secondmaterial layer comprises a first portion in direct contact with thefirst sidewall and a second portion in direct contact with the secondsidewall; a first conductive line disposed adjacent to the first portionof the conformal second material layer along the first direction andextending lengthwise along a second direction that is substantiallyperpendicular to the first direction; a second conductive line disposedadjacent to the second portion of the conformal second material layeralong the first direction and extending lengthwise along the seconddirection; a third conductive line in direct contact with distal ends ofthe first and second conductive lines; and a fourth conductive line indirect contact with proximal ends of the first and second conductivelines.
 2. The semiconductor structure of claim 1, wherein the firstmaterial layer comprises titanium nitride.
 3. The semiconductorstructure of claim 1, wherein the conformal second material layercomprises a dielectric material.
 4. The semiconductor structure of claim1, wherein the first, second, third, and fourth conductive linescomprise a same composition.
 5. The semiconductor structure of claim 4,wherein the first, second, third, and fourth conductive lines comprisetitanium nitride.
 6. The semiconductor structure of claim 1, wherein thefirst, second, third, and fourth conductive lines comprise a samethickness.
 7. The semiconductor structure of claim 1, wherein a width ofthe first conductive line is substantially equal to a width of thesecond conductive line.
 8. The semiconductor structure of claim 1,wherein a width of the first conductive line along the first directionis substantially equal to a thickness of the third conductive line. 9.The semiconductor structure of claim 1, further comprising: ametal-insulator-metal capacitor disposed over the second region, whereina composition of a conductor plate of the capacitor is the same as acomposition of the first conductive line.
 10. A semiconductor structure,comprising: a resistor disposed on a surface, the resistor comprising: afirst electrode and a second electrode, and a first conductive line anda second conductive line extending between the first electrode and thesecond electrode, wherein the first and second electrodes and the firstand second conductive lines are formed of a same material.
 11. Thesemiconductor structure of claim 10, wherein the first and secondelectrodes and the first and second conductive lines have a samethickness.
 12. The semiconductor structure of claim 10, wherein a widthof the first conductive line is substantially equal to a thickness ofthe first electrode.
 13. The semiconductor structure of claim 10,wherein a width of the first conductive line is substantially equal to awidth of the second conductive line.
 14. The semiconductor structure ofclaim 10, further comprising: a dielectric layer, wherein the firstconductive line is isolated from the second conductive line by thedielectric layer.
 15. The semiconductor structure of claim 10, furthercomprising: a passivation layer over the resistor; a first via extendingthrough the passivation layer and in direct contact with the firstelectrode; and a second via extending through the passivation layer andin direct contact with the second electrode.
 16. The semiconductorstructure of claim 10, further comprising: a metal-insulator-metalcapacitor on the surface, wherein a composition and a thickness of aconductor plate of the capacitor are substantially the same as acomposition and a thickness of the first conductive line, respectively.17. A semiconductor structure, comprising: a resistor disposed on asurface, the resistor comprising: a first electrode and a secondelectrode, and two conductive lines extending between the firstelectrode and the second electrode; and a capacitor disposed on thesurface, the capacitor comprising: a first plate conductor, and a secondplate conductor over the first plate conductor, wherein a width of oneof the two conductive lines is substantially equal to a thickness of thesecond plate conductor.
 18. The semiconductor structure of claim 17,wherein the first and second electrodes and the two conductive lines areformed of a same material.
 19. The semiconductor structure of claim 18,wherein the material comprises titanium nitride, copper, cobalt, ortungsten.
 20. The semiconductor structure of claim 17, wherein the twoconductive lines and the second plate conductor are formed of a samematerial.